This invention relates to a method and apparatus for monitoring abnormality in the clock driver of an electronic apparatus. More particularly, the invention relates to a method and apparatus for monitoring abnormality in the clock driver of an electronic apparatus having a clock supply unit that supplies a clock signal and a plurality of function executing units to which the clock signal is applied for executing prescribed functions at an identical clock, wherein each function executing unit is provided with a clock driver which, on the basis of the clock signal, oscillates internally to reproduce a clock signal.
In an electronic-information-communication apparatus (hereinafter referred to simply as an "electronic apparatus") using a plurality of CPUs or an electronic apparatus in which it is required that a plurality of units be operated by a common clock, an important problem that has recently arisen is speeding up the operating clock in order to satisfy the need for higher processing speeds of the CPUs or individual units.
Though it is necessary to raise the speed of the clock in each unit (inclusive of CPUs), simply raising clock speed can cause the clock to undergo skewing (a phase shift) or jitter, depending upon the connection distance between units. This can lead to erroneous operation of the apparatus or have a highly deleterious effect upon the operation of the apparatus.
In order to solve this problem, the practice in the prior art is to mount a clock driver on each clock sending/receiving unit. A clock between units is produced by internal oscillation of the clock driver. Alternatively, a low-speed clock is transmitted between units and the necessary high-speed clock is reproduced by internal oscillation of the clock driver.
FIG. 9 is a block diagram illustrating a conventional electronic apparatus of this kind. Numeral 1 denotes a clock supply unit for supplying a clock signal, and numerals 2, 3 represent a plurality of function executing units for executing prescribed functions at an identical clock. These units have clock drivers (CLK DRV) 1a, 2a, 3a, . . . , respectively, each of which is constituted by a PLL circuit (phase-locked loop circuit), by way of example.
The clock supply unit 1 includes a standard-frequency oscillator 1b that produces a signal on the basis of which the clock driver 1a generates a clock signal CL1 transmitted to the function executing units 2, 3, . . . via lines L1, L2, . . . , respectively.
The function executing units 2, 3, . . . receive the clock signal CL1 and generate, by internal oscillation, clocks CL2, CL3, . . . , respectively, used within the respective units. The clocks CL2, CL3, . . . are supplied to the CPUs, 2b, 3b, . . . and other circuit within the respective units. The units execute prescribed functions on the basis of the clock signals CL2, CL3.
In accordance with this arrangement, the effects of skewing and jitter can be eliminated by slowing down the frequency of the clock signal CL1 supplied by the clock supply unit 1, and generating the high-speed clock signals CL2, CL3, . . . on the side of the function execution units based upon the low-speed clock signal CL1.
In this arrangement in which each unit is provided with a clock driver, a malfunction in the clock driver of any unit can result in the clock not being outputted or in output of a clock having a fluctuating phase. When this occurs, the CPU or circuitry using this clock will operate erroneously. In the prior art, therefore, unit failure is detected by monitoring the operation of the CPU or circuitry.
Recent years have seen greater demand for an improvement in apparatus reliability and for shorter recovery time. Thus there is need for a function through which it is possible to judge which part in a unit is malfunctioning, as well as a function through which a changeover is made to a separately provided spare clock driver when the other clock driver fails.